Module D: Testing of electronic circuits

Course description

INTRODUCTION:

Role of testing, digital, analog and mixed signal test, VLSI technology trends affecting testing.

 

VLSI TESTING PROCESS AND TEST EQUIPMENT:

How to test chips? Types of testing, automatic test equipment.

 

TEST ECONOMICS AND PRODUCT QUALITY:

Test economics, costs of testing, yield,  defect level,  defect level estimation.

 

FAULT MODELING:

Types of defects, faults and errors, functional and structural testing, single stuck-at and multiple faults model, bridging fault model.

 

LOGIC AND FAULT SIMULATION:

Circuit modelling for logic simulation at different levels, algorithms for logic simulation, algorithms for fault simulation.

 

AUTOMATIC TEST-PATTER GENERATION:

Definition of test-pattern generator, redundancy identification, systems for automatic test pattern generation, testing of synchronous and asynchronous sequential circuits.

 

MEMORY TEST:

Failure analysis, test methods of memory devices.

 

ANALOG AND MIXED-SIGNAL TEST:

Functional DSP-based testing, test methods of ADC and DAC devices, model-based testing.

 

DELAY TEST:

Delay test problem, delay test methodologies, practical considerations in delay testing.

 

TEST IDDQ:

IDDQ test principle and survey of IDDQ methods, effectiveness and limitations of IDDQ test.

 

DESIGN FOR TESTABILITY:

DFT methods and DFT rules, scan design rules, scan and partial-scan design, variations of scan designs.

 

BUILT-IN SELF-TEST (BIST):

The economic case of BIST, test-pattern generation for BIST, test points insertion, memory BIST.  

 

BOUNDARY SCAN STANDARD:

Purpose of standard, circuit configuration with boundary standard IEEE 1149.1 (JTAG), analog test bus (ATB), targeted analog faults, boundary scan in analog circuits.

 

 

SYSTEM TEST

System test and core based design, functional and diagnostic test (fault dictionary, diagnostic tree, a microprocessor system test example), test architecture for system-on-a-chip (SOC).

Course is carried out on study programme

Elektrotehnika 2. stopnja

Objectives and competences

  • to acquire the knowledge of reasons for circuit defects, errors and faults, their detection and diagnosis,
  • knowledge on fault modelling for various design errors and circuit implementation defects,
  • knowledge of fault simulation and automatic testpattern generation algorithms,
  • knowledge of algorithms and methods for delay testing,
  • to master techniques for circuit design for testability,
  • practical approaches of design and test of electronic circuits.

Learning and teaching methods

  • lectures (slides and blackboard)
  • laboratory assignments (hands on fault detection and fault diagnosis in digital, analog and mixed-signal integratedcircuits.

Intended learning outcomes

After successful completion of the course, students should be able to:

 

  • understand the role of testing in design and implementation of electronic circuits,
  • select  suitable method for testing the electronic circuit,
  • testing operation of electronic circuit,
  • fault diagnosis in case of faulty behaviour,
  • design for circuit testability.

Reference nosilca

1. MOČNIK, Jure, ŽEMVA, Andrej. Controlling voltage profile in smart grids with remotely controlled switches. IET generation, transmission & distribution,  2014, vol. 8, no. 8, str. 1499-1508.

2. TOMAŽIČ Jure, ŽEMVA, Andrej. Efficient and lightweight battery management system contributes to victory in the Green Flight Challenge 2011. Electric power systems research, 2013, vol. 98, no. 5, str. 70-76.

3. MOČNIK, Jure, HUMAR, Janez, ŽEMVA, Andrej. A non-conventional intrument transformer. Measurement, 2013, vol. 46, no 10, str. 4114-4120.

4. SLUGA, Janez, ZALETELJ, Viktor, ŽEMVA, Andrej.  Agent control for reconfigurable open kinematic chain manipulators. International journal of advanced robotic systems, 2013, vol. 10, no. 353, str. 1-13.5. BAŠA, Kristjan, ŽEMVA, Andrej.Simulation and verification of a dynamic model of the electric forklift truck. Intelligent automation and soft computing, 2011, vol. 17, no. 1, str. 13-30.

5. BAŠA, Kristjan, ŽEMVA, Andrej. Simulation and verification of a dynamic model of the electric forklift truck. Intelligent automation and soft computing, 2011, vol. 17, no. 1, str. 13-30.

Study materials

1. GIZOPOULOS, Dimitris (Ed.). Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006.

2. WUNDERLICH, Hans-Joachim. Models in Hardware Testing, Springer Verlag, 2010.

3. BUSHNELL, Michael, AGRAWAL, Wishwani. Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits, Springer Publishing Company, 2013.

4. NAVABI, Zainalabedi. Digital System Test and Testable Design: Using HDL Models and Architectures, Springer, 2011.

Bodi na tekočem

Univerza v Ljubljani, Fakulteta za elektrotehniko, Tržaška cesta 25, 1000 Ljubljana

E:  dekanat@fe.uni-lj.si T:  01 4768 411